The present invention pertains to an apparatus for polishing wafers, and in particular to the polishing apparatus which is suitably used to manufacture a large-diameter wafer in which the required flatness of the surface of the wafer must be less than 0.5 micron rule in order to be useful in the manufacture of ULSIs (Ultra Large Scale integrated Circuits).
The requirements of typical half-micron rule ULSIs, for example, for 16M DRAM (Dynamic Random Access Memory), are large wafer diameter and extreme flatness. Wafers must be at least 200 mm in diameter, and the flatness thereof must meet the requirements of photolithography.
However, it has been found that in conventional wafer manufacturing methods, it is difficult to obtain sufficient flatness of the wafer. Namely, in the manufacture of wafers 200 mm or more in diameter, the requirements of the flatnesses of the wafers are very strict compared with those for the manufacture of wafers of smaller diameters. In particular, when a photolithographic process is utilized, the smaller the line width rule, the shallower the depth of focus becomes. Therefore, as the line width of an exposure is reduced, the flatness requirements increase. For instance, 16M devices have been produced using a tilting mechanism requiring a local flatness of less than 0.5 .mu.m in a 25 mm.times.25 mm area of the front wafer surface. Of course, higher global flatness and total flatness (back surface reference flatness) are also required.
To meet these requirements, it is particularly important to improve the polishing process during wafer manufacture. For example, Japanese Patent Application, Laid-Open No. 5-152262, discloses a wax-mount process in which large carrier plates of higher flatness are utilized to adhere wafers to be polished. The process is conducted in a higher grade cleanroom, and special care is taken to clean carrier plates and wafers to reduce the number of particles sandwiched between the carrier plate and the wafer in the wax. Additionally, wax thickness is reduced to improve flatness.
It is well-known that the particles sandwiched between the carrier plate and the wafer in the wax are the cause of "dimples" on the front surface of the wafer after demounting from the carrier plates. A dimple is a shallow depression with gently sloping sides that exhibits a concave, spheroidal shape, and these dimples are often overlooked during unaided visual inspection, and the presence of these dimples reduces the degree of flatness of chips for 16M. However, such defects may be easily detected using Makyo (parallel beam reflection image).
Unfortunately, the aforesaid process cannot eliminate dimple defects. By reducing the wax thickness to improve flatness, protrusions and ripples on the back surface cause dimple and wave defects on the front surface. Protrusions on the back surface are the locations at which adhered particles are protected from being etched-off during etching processing, and ripples result because etching processings cannot be performed uniformly over the entire surface although many attempts have been made, for example, by rotating wafers in the etching solution.
Further attempts at improvement of the etching process have been unsuccessful, but the inventors have resolved the aforesaid problems by developing a half-polishing method which involves removing protrusions and half-cutting peaks of ripples by polishing to improve flatness of back surface.
Furthermore, when a wafer is provided with a polysilicon film for extrinsic gettering, it is inevitable that so-called "mound" defects are created by particles or flakes falling on the wafers during the polysilicon CVD (Chemical Vapor Deposition) process, and also that irregularities of film thickness result due to irregularity of gas flow and ripples on the wafer surface. When wax-mounting a wafer with CVD polysilicon film and then polishing, irregularities on the back surface cause defects on the front surface, such as dimples and waves, and thereby deteriorate flatness. Therefore, by the half-polishing technique which involves eliminating mounds and cutting peaks of the ripples in a degree not exceeding the film thickness so as not to expose the inner wafer, a flatter back surface is obtained. By wax-mounting and polishing the above half-polished wafer, excellent flatness can be obtained.
Another effect of half-polishing the back surface of a wafer, in particular, a wafer with polysilicon film, is a noticeable decrease of particles during the succeeding process and during wafer transportation. This effect is supposed to reduce the breakage of protrusions or mounds and also reduce the peeling off of peaks of ripples or films by smoothing the back surface of the wafer. It is obvious that these effects are similar in the device manufacturing process.
The same effects appear in wafers polished on both sides (both sides polished simultaneously by a double side polishing machine). However, a wafer polished on both sides is not used because the back surface easily becomes dirty or scratched. Recently, it has been discovered that the contaminants adhering to the back surface are harmful when they migrate to the front surface and degrade submicron devices. Furthermore, misalignment of the back surface which may occur because it is difficult to distinguish the front surface from the back surface, may be overcome by optically distinguishing the mark on the front surface. It is therefore necessary to procure wafers polished on both sides.
However, important disadvantages appear during the photolithography process. It is obvious that the flatness of the vacuum chuck must be improved in order for highly integrated circuits to be sufficiently flat on the front surface to satisfy a shallow focus. Consequently, extremely flat surfaces are in contact with each other, strong adhesion occurs due to van der Waals forces, and it often happens that air cannot be completely eliminated, resulting in the formation of air bubbles between the chuck and the back surface. On the front surface, mounds appear above the location of air bubbles and deteriorate flatness in a manner similar to that when wafer flatness is poor. Furthermore, it becomes difficult to dismount the wafer from the vacuum chuck. To overcome these difficulties, it is necessary to construct complicated chuck structures having many vacuum holes and to slowly remove air from the inner portion to the outer portion. This considerably reduces the throughput of device production.
In contrast, a wafer provided with a half-polished back surface is almost of the same reflectivity as one having an etched surface, and is easily distinguished by the unaided eye. During lithography, the half-polished back surface is similar to an as-etched back surface because the troughs of the ripples function as conduits to allow the passage of air. There are therefore no difficulties during vacuum chucking and removal from the chucking. In view of the above, a wafer having a half-polished back surface has advantages similar to those of a wafer polished on both sides.
As described above, the half-polishing operation which involves eliminating mounds and cutting peaks of the ripples should be carried out in order to manufacture a large-diameter wafer exhibiting an excellent flatness. However, the constructions of any conventional wafer-polishing apparatuses are unsuited to such an operation.